• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    PURPOSE: An audio processing device for a DVC system is provided to restrain the use of internal memory such as a FIFO in the case of deshuffling of audio data in a DVC decoding system and reduce the number of external memory accessing, thereby effectively managing the inner and outer memories. CONSTITUTION: An audio processing device for a DVC system includes an input FIFO part(201) for storing and outputting audio samples by a synchronizing blocking unit, a memory address control part(204) for storing data output from the input FIFO part to an external memory(104), and an output FIFO part(205) reading the sample data from the memory via the memory address control part and storing the sample data after realignment according to the output. Input/output FIFO control parts(202,206) respectively control addresses of the input/output FIFO parts. An audio output interface part(207) outputs the data output from the output FIFO part for decoding.
    公开号:KR20030080262A
    申请号:KR1020020018676
    申请日:2002-04-04
    公开日:2003-10-17
    发明作者:정태일
    申请人:엘지전자 주식회사；
    IPC主号:
    专利说明:

    Audio processing apparatus of DVC system {Apparatus for processing audio in DVC system}
    [15] BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for reproducing a digital video camera (hereinafter referred to as DVC), and more particularly, to an audio processing apparatus that efficiently deshuffles audio data input by shuffling. will be.
    [16] Recently, the spread of home video is spreading, especially in digital camcorders.
    [17] Video and audio data from digital camcorders are compressed, aligned, and recorded on tape in a way that conforms to the DVC decoding system standards, and today's systems typically use a analog cable to connect a player that uses the camcorder's decoding capabilities to a TV to record recorded data. You see.
    [18] In addition, digital broadcasting has recently begun to be implemented in various countries, and the spread of digital versatile discs (DVDs) and the like has spread, and various digital A / V (audio / video) devices have been introduced. These digital systems have a digital input interface via IEEE 1394 as an add-on, which allows the digital camcorder's data to be received in digital form and then decoded within the system for better image quality. In addition, a digital TV (DTV) or other video system having an IEEE 1394 digital high-speed interface can implement a simple editing system if the decoding function complies with the DVC decoding system standard.
    [19] On the other hand, the DVC decoding system has a plurality of DIF sequences in each video frame unit, for example, 10 tracks (ie, DIF sequences) in the NTSC system and 12 tracks (ie, DIF in the PAL system). Sequence).
    [20] In addition, decoding and editing are possible in units of the above frames.
    [21] Each track is further composed of 150 DIF blocks. Each DIF block includes headers and sub code blocks SC0 and SC1, various additional data blocks VA0 to VA2, nine audio sync blocks A0 to A9, and 135 videos as shown in FIG. It consists of sync blocks V0 to V134.
    [22] In the DVC decoding system having such a data structure, shuffling is performed in order to minimize loss of A / V data due to an error together with a process for compressing data during data recording.
    [23] In this case, for audio data, shuffling is performed in units of samples within one video frame.
    [24] That is, the audio data in the DVC decoding system has two modes of 48k, 44.1k, and 32kHZ according to the sampling rate, and the amount of audio data in one frame differs in the number of samples according to each mode. Each typical sample consists of 16 bits (= 2 bytes) of data, and in the case of 32kHZ sampling, there is also a 24-bit mode per sample that reorders the data (this mode is referred to below as 32k-2 channel mode). As long as the unit is shuffled, the number of audio samples in a video frame may have a maximum of 1620 in the 48kHZ sampling mode. In the case of 32k-2 channel mode, after deshuffling, the data is restored to 32 bits per sample. Therefore, it is necessary to process up to about 3800 bytes of data.
    [25] That is, the position shuffled within one frame is determined by a track number (TN), a sync block number (SBN), a byte position number (BPN), and a track number, a sync number, And byte location numbers are determined by certain specifications.
    [26] For example, according to the specification of the 48KHz 525/60 system two-channel mode, the track number, sync block number, and byte position number are determined according to the rules shown in the following equation.
    [27] TN = (int (J / 3) + 2 x (J MOD 3)) MOD 5 ---- 1st channel
    [28] TN = (int (J / 3) + 2 x (J MOD 3)) MOD 5 + 5 ---- 2nd channel
    [29] SBN = 3 x (J MOD 3) + int ((J MOD 45) / 15)
    [30] BPN = 2 x int (J / 45) ----- Upper Byte
    [31] BPN = 2 x int (J / 45) + 1 ----- Lower Byte
    [32] In the above formula, J is a sample index, that is, a sample number in one frame, MOD means Modulo operation, and int means taking an integer only.
    [33] The pattern shown by shuffling in the 48 KHz mode by such a rule is as shown in FIG. 2.
    [34] For example, when the track number TN is '0' or '5', shuffling as shown in Fig. 2A according to the sync block number SBN (i) and the byte position number BPN (j). If the track number TN is '1' or '6', shuffling as shown in Fig. 2B according to the sync block number SBN (i) and the byte position number BPN (j). If the track number TN is '2' or '7', the shuffling as shown in Fig. 2C according to the sync block number SBN (i) and the byte position number BPN (j). If the track number TN is '3' or '8', the shuffling as shown in FIG. 2D according to the sync block number SBN (i) and the byte position number BPN (j) If the track number TN is '4' or '9', the shuffling as shown in FIG. 2E according to the sync block number SBN (i) and the byte position number BPN (j) It becomes a pattern.
    [35] Accordingly, a process of shuffling an audio sample will be described with reference to FIG. 2.
    [36] In other words, the 48KHz 525/60 two-channel mode system uses NTSC to record channel 1 on the first five tracks and channel 2 on the latter five tracks. Record it.
    [37] Thus, the first audio sample D0 of the two channels is recorded in the tenth and eleventh bytes of the second sync block of the tracks '0' and '5', and the second audio sample D1 of the two channels is '2'. The tenth and eleventh bytes of the fifth sync block of the 'and' 7 'tracks are recorded, and the third audio sample (D2) of the two channels is the tenth and tenth of the eighth sync block of the' 4 'and' 9 'tracks. The fourth audio sample (D3) of the two channels is recorded in the eleventh byte, and the tenth and eleventh bytes of the second sync block of the tracks '1' and '6' are recorded, and the fifth audio sample of the two channels ( D4) The tenth and eleventh bytes of the fifth sync block of the '3' and '8' tracks are recorded.
    [38] According to this specification, each audio sample J is recorded and shuffled.
    [39] In this case, since the unit of shuffling is one frame (that is, the data of the entire frame area is slightly input for each input unit), the internal memory corresponding to 3800 bytes must be provided to process it at once.
    [40] Therefore, in the case of employing the DVC function as part of a function in a non-memory semiconductor device including a digital video decoder or a central processing unit, such internal memory size may be burdensome to minimize the size of the entire block.
    [41] In addition, even when the shuffling is performed through the external memory, if the read / write unit is performed in the sample unit, the use of the external memory becomes inefficient, which may cause problems when it is necessary to operate with various functions of other blocks at once.
    [42] For this reason, an efficient deshuffling method is required for the audio processing of the DVC system, although the processing ratio is relatively small.
    [43] An object of the present invention is to process audio in a DVC system that efficiently processes deshuffling of audio data when receiving compressed and shuffled data in a digital interface and decoding and deshuffling according to the DVC decoding standard to restore original data. In providing a device.
    [1] 1 is a diagram illustrating a data structure of each DIF block in a general DVC system.
    [2] 2A to 2E illustrate an example in which samples of audio data of FIG. 1 are shuffled according to a predetermined specification.
    [3] 3 is a block diagram of an audio processing device of a DVC system according to the present invention;
    [4] 4A shows an example of input of shuffled audio data in one sync block;
    [5] 4B is a diagram illustrating an example of the order of audio data written to the external memory of FIG. 3.
    [6] 4C is a diagram illustrating an example of a sequence of audio data read from the external memory of FIG. 3.
    [7] FIG. 5 is a detailed block diagram of the output FIFO controller of FIG. 3. FIG.
    [8] Explanation of symbols for main parts of the drawings
    [9] 101: 1394 digital interface 102: system demultiplexer
    [10] 103: memory arbiter 104: external memory
    [11] 200: audio processing unit 201: input FIFO unit
    [12] 202: input FIFO control unit 203: data reordering unit
    [13] 204: memory address control unit 205: output FIFO unit
    [14] 206: output FIFO control unit 207: audio output interface
    [44] The audio processing apparatus of the DVC system according to the present invention for achieving the above object, the input FIFO unit for storing and outputting the shuffled and input audio samples in sync block units, and the decode of audio samples corresponding to one frame An external memory for storing audio samples output from the input FIFO unit by dividing into a plurality of areas and assigning a bank to each of the regions after shuffling, and an external memory write for storing data read from the input FIFO unit in an external memory A memory address controller which generates an address and generates and outputs an external memory read address to sequentially read samples included in a current processing section according to a deshuffling processing unit, and outputs from an external memory through the memory address controller Output audio sample data And an output FIFO unit and outputting the position rearranged to suit, it is characterized in that comprises the output interface for outputting the audio output for decoding the data output from the FIFO portion.
    [45] The audio processing apparatus of the DVC system may further include a data rearranging unit for restoring the input audio data into 16-bit sample data of two channels by expanding from 12 bits to 16 bits in the 32k-2 channel mode.
    [46] The audio processing apparatus of the DVC system may further include an input FIFO control unit controlling a write address of the input FIFO unit and an output FIFO control unit controlling a read address of the output FIFO unit.
    [47] The output FIFO control unit includes an index counter for generating a sample index up to a maximum sample number corresponding to a current mode, a track number generator for generating a track number at which the sample index is located by applying the sample index to an audio shuffling rule; Generating a read address of the output FIFO unit by using the sync block number generator generating the sync block number at which the sample index is located by applying the sample index to an audio shuffling rule, and using the track number and the sync block number. An output FIFO read address generator and an output FIFO selection signal generator for generating a signal for selecting one of four output FIFOs forming one stage in the output FIFO unit according to the sample index and outputting the signal to the output FIFO unit It is characterized by.
    [48] When the output FIFO selection signal generator assumes that the number of samples in the sync block unit is S, whether the sample index in the input sync block is greater than or less than S / 2, and is the even numbered value of the sync block of the audio only It is characterized in that the selection signal is generated according to the odd number.
    [49] Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.
    [50] Hereinafter, with reference to the accompanying drawings illustrating the configuration and operation of the embodiment of the present invention, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, By the technical spirit of the present invention described above and its core configuration and operation is not limited.
    [51] FIG. 3 is a block diagram illustrating an audio processing apparatus in a DVC system according to the present invention, and includes a first input first output (FIFO) unit 201 for storing audio samples shuffled and input according to a specification. An input FIFO control unit 202 for controlling an address of the input FIFO unit 201, a memory address control unit 204 for storing data output from the input FIFO unit 201 in an external memory 104, and the memory address An output FIFO controller 205 for rearranging and storing positions according to the output while reading sample data from the memory 104 through the controller 204, and an output FIFO controller 206 for controlling an address of the output FIFO module 205; And an audio output interface unit 207 for outputting the data output from the output FIFO unit 205 for decoding.
    [52] At this time, in the 32k-2 channel mode, 3 bytes (24 bits) of data are input per sample, but this is restored to 2 channels of 16 bit samples, that is, 32 bits of data by decompressing from 12 bits to 16 bits. It has a data reordering unit 203. The data reordering unit 203 may be disposed between the system multiplexer 102 and the input FIFO unit 201 or between the output FIFO unit 205 and the audio output interface unit 207. When the data reordering unit 203 is disposed in front of the input FIFO unit 201, subsequent memory 104 read / write and deshuffling processes are made of reconstructed data. If the data rearranging unit 203 is disposed at the rear end of the output FIFO unit 205, the data rearranging unit 203 restores 32-bit data from the data rearranging unit 203 (dotted block) to the deshuffled data. The external audio output interface unit 207 is output.
    [53] In addition, a 1394 digital interface 101 and a system demultiplexer 102 are provided at an input side of the audio processor 200, and between the memory address controller 204 and the external memory 104 of the audio processor 200. A memory arbiter 103 for storing data output through the memory address control unit 204 in the order of priority or reading data from the memory 104 and outputting the data to the memory address control unit 204 is provided. .
    [54] In the present invention configured as described above, the video / audio data input through the 1394 digital interface 101 is separated into video and audio data in the system demultiplexer 102. In this case, the video data is output to the video decoder, and the audio data is output to the audio processor 200 for deshuffling. 4A illustrates an example in which audio data shuffled in one sync block is input to the audio processor 200.
    [55] That is, as shown in FIG. 4A, the audio data shuffled and input according to the specification is deshuffled by the audio processor 200 until it is output through the audio output interface 209, and is output in synchronization with the video signal output. The process of being stored in the memory 104 and outputting is controlled.
    [56] In the present invention, a case where the data reordering unit 203 is disposed in front of the input FIFO unit 201 will be described as an embodiment. That is, when the audio data output from the system multiplexer 102 is in 32k-2 channel mode, 3 bytes (24 bits) of data are input per sample, and the data rearranging unit 203 uses 12 bits to 16 bits. By decompressing, three bytes of data per sample are restored to two channels of 16-bit samples, that is, 32 bits (two bytes) of data, and then output to the input FIFO unit 201.
    [57] Here, the audio processor 200 processes audio data in units of sync blocks, and a sync block of the audio data is input once between 15 sync blocks of video data as shown in FIG. 1.
    [58] Accordingly, the input FIFO unit 201 stores audio data as a sync block corresponding to a processing unit in one stage, and then receives an external memory (or memory) through the memory address control unit 204 between the next audio sync block. 104).
    [59] Alternatively, the processing of storing in the external memory 104 while 15 video blocks are input for the implementation of a system in which there are several memory access units and blocks requiring relatively urgent memory access depending on the situation of the entire system If it is not guaranteed, the input FIFO unit 201 may be provided in two stages so that read and write may be simultaneously performed. That is, while data is written to one end of the input FIFO unit 201, the other end outputs the pre-stored data to an external memory, and after the process is performed, the stored data is alternately output to the external memory. At the same time, the data stored in the previous step is output to the external memory, and the process of writing the input data is repeated.
    [60] At this time, the size of one stage of the input FIFO unit 201 for storing the input audio data is the width of the external memory access data bus of the system (MW) and the number of times that can be continuously written in one memory access (MC). It can be determined according to the internal standard that restricts. That is, the length is determined according to the number of sync blocks to be stored at one time in consideration of MC having a width corresponding to MW / 2.
    [61] In the first embodiment of the present invention, in a system having an MW of 64, audio corresponding to two sync blocks is processed as one continuous external memory write access. In this case, the length is set to 64 considering two channel modes.
    [62] To this end, in the input FIFO controller 202, when the first sync block is input as shown in FIG. 4B, data input by 32 bits (that is, two samples) are sequentially stored in the left FIFO of the input FIFO unit 201. When the first sync block is input, it is controlled to be stored in the right FIFO.
    [63] Accordingly, an arrangement of data output from the input FIFO unit 201 to store data stored in the input FIFO unit 201 in the external memory 104 is the same as the example of FIG. 4B.
    [64] In this case, the memory address control unit 204 for controlling the write / read address of the memory 104 may include a memory write / read address generator (not shown) for writing data to or reading data from the external memory, and an input FIFO. The unit 201 includes an input FIFO read address generator (not shown) for reading data.
    [65] At this time, the external memory 104 is divided into B areas according to the position after deshuffling of samples corresponding to one frame, and a bank is allocated to each of them. That is, B is the number of banks of the external memory.
    [66] In addition, the external memory write address generator in the memory address control unit 204 generates a write address to write data corresponding to 'minimum integer greater than or equal to CN = [72 / MW]' in one sync block. For each bank, an address is generated to write consecutive data corresponding to the division of the memory area by B. Here, the number of samples of one sync block is 36, and one sample is two bytes, so one sync block has 72 bytes.
    [67] The external memory read address generator in the memory address control unit 204 generates a read address to sequentially read the samples included in the current processing section in accordance with the minimum deshuffling processing unit. For example, in 48 / 44.1 / 33k mode, there are 36 areas, so you can read one and skip 35 column addresses.
    [68] The data read from the position in the external memory 104 corresponding to the read address is written while generating addresses sequentially in the output FIFO unit 205 under the control of the output FIFO control unit 206. At this time, when the data deshuffled by the signal of the audio output interface unit 207 is sent to the outside, the read address of the output FIFO unit 205 is generated according to the order in which the deshuffling is completed. You can control which data is sent.
    [69] The size of the output FIFO unit 205 may be determined by the minimum unit in which final deshuffling is performed.
    [70] The output FIFO control unit 206 reads data from the output FIFO unit 205 having one or two stages, and outputs the data simultaneously with deshuffling. In this case, the output FIFO may be used in two stages to output an analog audio signal using only a D / A (Digital / Analog) converter without using an external buffer. In the present invention, an embodiment using two stages of an output FIFO having a length of 32 with a value close to 27 is used. 27 is a value corresponding to half of 54, which is a positional difference between successive data values for shuffling a 625-50 system with a greater amount of data.
    [71] Each output FIFO stage in the output FIFO section 205 is composed of four FIFOs having a 16-bit width as shown in FIG. 4C to allow sample access for deshuffling.
    [72] At this time, the deshuffling is performed by the output FIFO controller 206. The output FIFO unit generates a read address according to the audio shuffling rule of 62843-2 while increasing the sample index J in accordance with the minimum deshuffling unit. Read data from the selected output FIFO in 205.
    [73] FIG. 5 is a detailed block diagram of an output FIFO control unit 206 which controls the output FIFO unit 205 to perform deshuffling. An index counter that sequentially generates an index J up to a maximum sample number suitable for a current mode is shown in FIG. 301, a track number generator 302 for generating a track number TN using the sample index J output from the index counter 301, and a sync block number SBN using the sample index J Generates a read address of the output FIFO unit 205 using the sync block number generator 303, the track number TN, and the sync block number SBN, and outputs the read address to the output FIFO unit 205. An output for generating a signal for selecting any one of a plurality of output FIFOs in the output FIFO in one stage according to an output FIFO read address generator 304 and the sample index J and outputting the signal to the output FIFO unit 205 With FIFO select signal generator 305 It is sex.
    [74] The index counter 301 sequentially generates the sample index J according to the channel. For example, in the 48 / 44.1 / 33k mode, the sample index J increases from 0 to 1619. The sample index J is output to the track number generator 302, the sync block number generator 303, and the output FIFO selection signal generator 305. The track number generator 302 and the sync block number generator 303 apply the sample index J to the audio shuffling rule of 62843-2 to obtain a track number (ie, a DIF sequence number) and a sync block number.
    [75] That is, the track number generator 302 applies the sample index J to Equation 1 to generate the track number TN where the sample index J is located, and the sync block number generator 303 Applying the sample index (J) to the above equation (2) to generate a sync block number (SBN) in which the sample index (J) is located to the output FIFO read address generator 304 and the output FIFO selection signal generator 305 Output
    [76] The output FIFO read address generator 304 obtains the order C in the sync block by applying the track number and sync block number to Equation 4 below to generate an output FIFO read address D, and then outputs the FIFO unit 205. )
    [77] C = (track number MOD 5) * 9 + sync block number-for 525-60 systems
    [78] D = C / 2
    [79] The output FIFO selection signal generator 305 generates a selection signal for selecting any one of a plurality of output FIFOs (for example, four output FIFOs) forming one stage of the output FIFO unit 205. Output to output FIFO section 205.
    [80] The rule for selecting one output FIFO from the four output FIFOs forming one stage in the output FIFO selection signal generator 305 is a sample index in the minimum sync block that is input when S is the number of samples in the minimum block unit. Is selected according to whether C is greater than or less than S / 2 and the C value is even or odd.
    [81] Here, the sample index in one sync block can be obtained by applying J mod S (= J value increases again from 0 when the sequentially increasing J value exceeds S. S is the number of samples in one sync block). have. Then, C mod 2 is used to check whether the C value is even or odd.
    [82] That is, when the sample index in the input minimum sync block is smaller than S / 2 and the C value is an odd number, the data corresponding to the read address generated by the output FIFO read address generator 304 is inputted from the first output FIFO. In case of even number control, it reads from the third FIFO.
    [83] In addition, when the C index is an odd number when the sample index in the input minimum sync block is greater than or equal to S / 2, the data corresponding to the read address is read from the second output FIFO and the fourth FIFO if the even number is odd. Control to come.
    [84] 5 is an example of a 525-60 system and is selected according to a sample rate and an application mode. The dotted lines in FIG. 4A represent the range constituting the minimum deshuffling unit.
    [85] As described above, the present invention can implement the deshuffling process of audio along with the external memory read and write process by using an effective amount of FIFO and external memory access.
    [86] As described above, according to the audio processing apparatus of the DVC system according to the present invention, the internal memory and the external memory by reducing the number of external memory accesses while limiting the use of internal memory (eg, FIFO) when deshuffling audio data in the DVC decoding apparatus Can be managed efficiently. That is, the use of the block size and the memory bandwidth for deshuffling can be minimized.
    [87] Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.
    [88] Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.
    权利要求:
    Claims (10)
    [1" claim-type="Currently amended] An input FIFO unit for storing and outputting the shuffled and input audio samples in sync block units;
    An external memory configured to store audio samples output from the input FIFO unit by dividing into a plurality of areas according to positions after deshuffling of audio samples corresponding to one frame, and assigning banks to each one;
    Generate an external memory write address for storing data read from the input FIFO unit in an external memory, and generate an external memory read address to sequentially read samples included in a current processing section according to a deshuffling processing unit A memory address controller for outputting;
    An output FIFO unit for storing the audio sample data output from the external memory through the memory address control unit and rearranging the positions according to the output order; And
    And an audio output interface unit for outputting the data output from the output FIFO unit for decoding.
    [2" claim-type="Currently amended] The method of claim 1,
    The audio processing apparatus of the DVC system, characterized in that the input audio data further comprises a data rearranging unit for restoring the 16-bit sample data of the two channels by the extension from 12 bits to 16 bits in the case of 32k-2 channel mode.
    [3" claim-type="Currently amended] The method of claim 2, wherein the data reordering unit
    The audio processing apparatus of the DVC system, characterized in that disposed in front of the input FIFO unit, or disposed in the rear end of the output FIFO unit.
    [4" claim-type="Currently amended] The method of claim 1, wherein the memory address control unit
    When storing the data of one sync block in external memory, write the memory corresponding to 'CN (= [minimum integer greater than or equal to [data size / memory bandwidth of one sync block])' to the CN for each bank. An external memory write address is generated to write continuous data corresponding to the divided portion.
    [5" claim-type="Currently amended] The method of claim 1,
    The output FIFO unit is composed of at least one stage,
    Each stage of the output FIFO unit is composed of a plurality of FIFO having a width of one sample size, audio processing apparatus of the DVC system.
    [6" claim-type="Currently amended] The method of claim 1,
    An input FIFO controller for controlling a write address of the input FIFO unit;
    And an output FIFO controller for controlling a read address of the output FIFO unit.
    [7" claim-type="Currently amended] The method of claim 6, wherein the output FIFO control unit
    An index counter that sequentially generates a sample index up to the maximum sample number for the current mode,
    A track number generator for applying the sample index to an audio shuffling rule to generate a track number at which the sample index is located;
    A sync block number generator for applying the sample index to an audio shuffling rule to generate a sync block number at which the sample index is located;
    An output FIFO read address generator configured to generate and output a read address of the output FIFO unit using the track number and the sync block number;
    And an output FIFO selection signal generator for generating a signal for selecting one of four output FIFOs constituting one stage in the output FIFO unit and outputting the signal to the output FIFO unit according to the sample index in the minimum sync block. Audio processing unit in a DVC system.
    [8" claim-type="Currently amended] 8. The apparatus of claim 7, wherein the output FIFO read address generator
    And an output FIFO read address by applying the track number and the sync block number to the following equation.
    Output FIFO Read Address = ((Track Number MOD 5) * 9 + Sync Block Number) / 2
    [9" claim-type="Currently amended] 8. The apparatus of claim 7, wherein the output FIFO select signal generator
    If the number of samples in the sync block unit is S, the sample index in the input sync block is greater than or less than S / 2, and only the sync blocks are ordered ((track number MOD 5) * 9 + sync block number) And a selection signal is generated according to the even-numbered or odd-numbered number.
    [10" claim-type="Currently amended] 10. The apparatus of claim 9, wherein the output FIFO select signal generator
    If the sample index in the input sync block is less than S / 2 and the value of ordering only the sync block is an odd number, the data corresponding to the read address generated by the output FIFO read address generator is even in the first output FIFO. The second case generates a select signal to read from the third FIFO,
    If the sample index in the input sync block is greater than or equal to S / 2 and the value of ordering only the sync block is an odd number, the data corresponding to the read address generated by the output FIFO read address generator is output from the second output FIFO. And if the even number, generate the selection signal to read from the fourth FIFO.
    类似技术:
    公开号 | 公开日 | 专利标题
    US5594660A|1997-01-14|Programmable audio-video synchronization method and apparatus for multimedia systems
    KR100275060B1|2000-12-15|Multiple picture/sound signals decoding apparatus
    JP3864346B2|2006-12-27|Method and apparatus for synchronizing audio and video in an MPEG playback system
    US5583652A|1996-12-10|Synchronized, variable-speed playback of digitally recorded audio and video
    AU676012B2|1997-02-27|Dual memory buffer scheme for providing multiple data streams from stored data
    EP1187489B1|2007-08-29|Decoder and decoding method, recorded medium, and program
    KR100309654B1|2001-12-15|Methods and systems for compressing, positioning and partially reconstructing digital images
    KR960002393B1|1996-02-16|Recording and playing apparatus of image signal
    JP3134424B2|2001-02-13|Variable length encoding method and apparatus
    JP3877759B2|2007-02-07|Television receiver having buffer memory
    US5504585A|1996-04-02|Apparatus and method for providing plural pictures while searching a recording medium whereon a compressed picture signal is recorded
    US5796957A|1998-08-18|Network system and terminal apparatus
    US5758012A|1998-05-26|Digital video signal processing system for transmission and recording
    KR100606812B1|2006-08-01|Video decoding system
    JP3801198B2|2006-07-26|Recording and playback of MPEG information signals to / from record carriers
    US5699476A|1997-12-16|Method and apparatus for transmitting and/or storing a series of hierarchically encoded digital image data blocks
    EP0727912B1|2002-05-02|Reproduction of coded data
    KR100904626B1|2009-06-25|Trick play for MP3
    US5838380A|1998-11-17|Memory controller for decoding a compressed/encoded video data frame
    KR100230159B1|1999-11-15|Signal processor
    JP3686155B2|2005-08-24|Image decoding device
    US5487035A|1996-01-23|Method of multiplexed data reading/writing suitable for video-on-demand system
    EP1602235B1|2008-08-20|Generation of encrypted video information
    US6118821A|2000-09-12|Compressed code decoding device and audio decoding device
    US7394829B2|2008-07-01|Data multiplexing apparatus, data multiplexing method, and transmission apparatus
    同族专利:
    公开号 | 公开日
    KR100447190B1|2004-09-04|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    法律状态:
    2002-04-04|Application filed by 엘지전자 주식회사
    2002-04-04|Priority to KR10-2002-0018676A
    2003-10-17|Publication of KR20030080262A
    2004-09-04|Application granted
    2004-09-04|Publication of KR100447190B1
    优先权:
    申请号 | 申请日 | 专利标题
    KR10-2002-0018676A|KR100447190B1|2002-04-04|2002-04-04|Apparatus for processing audio in DVC system|
    [返回顶部]